3D processors, memory and storage explained

7th Aug 2011 | 07:00

3D processors, memory and storage explained

How 3D structures will offer a new level of performance

3D processors

Entering the third dimension has huge implications for a PC's display system, but it doesn't end with a high performance graphics card and a stereoscopic monitor. 3D images put great demands on the processor and its associated memory, and storing 3D content requires vast amounts of hard drive space.

It therefore seems appropriate that a major strand in current research is improving performance by making the components themselves three-dimensional in structure.

In May, Intel made a remarkable announcement - all its processors with a 22nm feature size and beyond will soon feature 3D transistors. Officially known as 3D Tri-gate transistors, these new circuit elements have a completely new structure that comes out of the plane of the chip, and offer increased performance and lower power consumption.

But this is just a start, as you'd discover if it were possible to take a ride in a miniature aircraft over the surface of the silicon die in a processor. You'd see an amazing landscape of hills and valleys, but first appearances can be deceptive.

All the transistors - even 3D ones - would be in one plane, connected horizontally. According to many researchers though, all this could be about to change as processors move to a multi-layered arrangement.

This approach will minimises the chip's 'footprint', and hence the size of the circuit board, which is vitally important in mobile computing. It will also provide a way to improve performance at a time when continually shrinking the feature size is becoming increasingly difficult.

Multi-layered chips

IBM multi-layered chips

PROTOTYPE CHIPS:IBM sandwiched cooling layers with water channels no wider than a human hair between layers of transistors

To see how this works, we spoke to Dr Bruno Michel, manager of Advanced Thermal Packaging at IBM Research in Zurich. "The main benefit of adopting a 3D structure is that the distances for information transport become far shorter than with 2D chips," he says.

"The second benefit is that more interconnects are possible, which further improves communication speed. The main problem of a current processor is that it takes on average 1,300 clock cycles for information to arrive from the main memory, which is some 20-30 cm away. This is partially alleviated by introducing cache memory on the processor chip, but during a 'cache miss', waiting is inevitable. In 3D chip stacks, cache memories can be much larger which reduces the waiting time and thereby considerably improves the overall efficiency."

None of this comes without some considerable challenges, the first of which is making those connections between the layers of transistors.

One method is to extend the layer-upon-layer fabrication method used today to create multiple layers of transistors with the necessary interconnections running both horizontally and vertically. This is called the monolithic approach.

Success here has been limited though, partly because the heat needed to create a new layer of transistors is often enough to destroy any connective pathways already in place. Although monolithic 3D chips could offer much greater connectivity, most of today's research has therefore been into methods of creating inter-layer connections between several wafers or dies that have been manufactured conventionally. Even this isn't without its challenges, as Dr Michel explains:

"The problem is tackled in several stages: The first is the development of the Through Silicon Via (TSV) technology, which allows chips to be stacked with short interconnect distances. This can be applied to systems that are composed of heterogeneous technologies with one chip being logic and other chips being cache memory".

In a similar vein, other researchers refer to stacking cores as a means of improving core-to-core communications.

Keeping cool

Dr Michel's second point isn't a new one, although a 3D structure exacerbates it. "The second development is the cooling technology needed, since stacking of logic chips multiplies the heat fluxes and thermal resistances with the number of layers. For this reason interlayer cooling will become mandatory when more than three processors are stacked."

IBM is addressing this issue by implementing water-cooling on a miniature scale. It has used cooling channels as thin as a human hair between the individual layers to achieve up to 180W of cooling per square centimetre on each layer.

3D memory and 3D data storage

3D memory

3D memory

3D SANDWICH:3D memory uses the same principle as 3D processors, with DRAM layers allowing for greatly increased density and efficiency

When you read this, Samsung's latest 8GB memory modules will be about to hit the market. Using the same TSV technique IBM pioneered to move processors into the third dimension, Samsung bonded memory chips together, allowing them to communicate vertically.

The company claims that its DDR3 DIMMs will offer a 50 per cent improvement in memory density, while providing a 40 per cent reduction in energy consumption compared to conventional memory modules.

Spectacular gains

The improvements promised by Samsung's dual-layer memory modules are relatively modest because they're designed to work in conjunction with ordinary processors and standard motherboards. If these constraints are removed though, much more spectacular gains can be achieved, as Dr Dong Hyuk Woo of the Georgia Institute of Technology explains.

"A CPU is typically manufactured with a logic process optimised for speed while a DRAM is typically optimised for density," he says. "Due to such different optimisation requirements, we weren't able to implement both components on the same silicon die or chip. Thus, each chip was manufactured into an individual package, and later mounted on the same motherboard to form a system. Such separation means the number of interconnects between these two packages has been seriously limited so data bandwidth between them was also limited. Such limited data bandwidth has been called a von Neumann bottleneck."

Fortunately, Dr Woo has a solution up his sleeve. "Now, on the other hand, 3D integration allows multiple dies, built with different manufacturing technologies, to be packaged and integrated into a single package," he says.

What's more, using TSVs means the number of parallel lines connecting the main memory to the top level cache could be phenomenal - as many as 32,000 has been suggested. In his research, Dr Woo was interested in how much performance can be improved with such tight integration, which can practically eliminate the bandwidth limitation.

Working on the basis of a one layer processor, one layer for the memory controller, and four layers for the memory, he was able to demonstrate that fetching huge chunks of data from main memory to cache didn't saturate the memory bandwidth. By using such an aggressive approach, he was able to show a doubling of processor performance in many instances.

But if this technology becomes mainstream, we would essentially be saying goodbye to RAM as a system component. In much the same way that Intel's Sandy Bridge processors have eliminated the Northbridge chip, GPU and memory controller by integrating them with the CPU, if Dr Woo's vision becomes a reality, this super-chip would also include the system memory.

Meanwhile, researchers at Rice University in Texas have developed a form of flash memory with two terminals per bit instead of the three in standard memory. The benefits go beyond its inherent simplicity; the two-terminal architecture is also more suitable for building into 3D arrays.

Rice University's Professor James Tour jokes, "I've been told by [the] industry that if you're not in the 3D memory business in four years, you're not going to be in the memory business. This is perfectly suited for that."

3D data storage

GE holographic disc

COMING SOON-ISH:Overlapping blue lasers are used to record holograms in a GE micro-holographic disc

Mass storage media is flat, but even today it's not entirely two-dimensional. DVD and Blu-ray discs can both have two layers of data per side, and researchers have demonstrated 16-layer disks (400GB). But there's a limit to how far the technology can be stretched.

Although the laser beam addresses a particular layer by tight focusing, passing through several other reflective layers can seriously degrade the signal.

Holography is a means of recording a scene so that it can be viewed from any angle, providing a true 3D experience. The same technique can be used to store pages of binary data, which are selected by altering the angle at which the hologram is read.

Although we can't talk about layers, the data in a hologram is spread through the thickness of the media. This has been touted as a future method of high capacity data storage for years, but companies intent on bringing products to the market have been unsuccessful. An announcement by General Electric of a micro-holographic disk is therefore particularly interesting.

By placing microscopic holograms on a 120mm disk, it offers a significant advantage, as GE's Brian Lawrence explains:

"Because GE's micro-holographic discs could be read and played using similar optics to those in Blu-ray players, our technology will pave the way for holographic drives that could be in every home. The day when you can store your entire HD movie collection on one disc and support formats like 3D TV is closer than you think."


First published in PC Plus Issue 310. Read PC Plus on PC, Mac and iPad

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